This invention generally relates to diagnostics of logical circuits and more particularly to a method and apparatus for diagnosis of a semiconductor memory and/or a combinational logical circuit having its input and output terminals respectively connected to latches which are operated by a single-phase clock signal.
A logical circuit having its input and output terminals respectively connected to latches operated by the same clock pulse contained in a single-phase clock signal is exemplarily constructed as illustrated in FIG. 1. Especially, in this example, an address latch (input latch) 2 and an output latch 3 of a semiconductor memory 1 are operated by a single-phase clock signal c. As an example, the clock signal c is illustrated in FIG. 2A. On the other hand, in the case where the circuit of FIG. 1 is operated using a multiphase clock signal, for example, a two-phase clock signal, respective clock terminals of the input and output latches 2 and 3 are separately supplied with two clock signals as shown at (1) and (2) in FIG. 2B. In the case of the multiphase clock signal, however, the width of clock pulses contained in one clock signal will often differ from that of clock pulses contained in another clock signal. Further, timing interval T.sub.0 observed at receiving points of the clock signals is often different or deviates from that observed at supply points of the clock signals due to the fact that the paths through which clock signals are sent are rarely identical. For example, different logical circuits such as some gate circuits inserted in such paths cause different clock-pulse transmission delays, causing such difference in the timing interval. Accordingly, with a relatively short timing interval T.sub.0, it is more advantageous to use the single-phase clock signal than to use the multiphase clock signal from the standpoint of the operating margin of logical circuits operated by clock pulses. Further, in designing logical circuits for use with a single-phase clock signal, the restriction of separate phase-component clock signals can advantageously be removed and the degree of freedom of design can be increased. Reference may be made to, for example, JP-A-58-83394 for a disclosure of techniques concerning a single-phase clock signal described above.
An exemplary method for diagnosis of the circuit of FIG. 1 operated by a single-phase clock signal is carried out in accordance with an operation timing chart as illustrated in FIG. 3. Successive sets of scan address input data A.sub.0 to A.sub.7, each set represented as N, N+1, N+2, . . . , are applied to a data input terminal D of the address latch 2 at timings as illustrated in FIG. 3. A set of scan address input data A.sub.0 to A.sub.7 represented as the scan address N are set into the address latch 2 by the rise (i.e. leading edge) of a clock pulse P1 contained in the single-phase clock signal c applied in common to clock input terminals C of the address latch 2 and output latch 3 and are substantially at the same time applied to address input terminals A.sub.0 ' to A.sub.7 ' of the semiconductor memory 1 through an output terminal Q of the address latch 2. The scan address data N is held in the address latch 2 by the fall (i.e. trailing edge) of the clock pulse P1 and this data N, now in the address latch 2, is replaced with the next data N+1 at the rise of the following clock pulse as designated by P2. After expiration of a delay time Td of the semiconductor memory 1, output data D corresponding to the input data N is delivered to an output terminal D.sub.o of the semiconductor memory 1. At the rise of the clock pulse P2 following the clock pulse P1, the output latch 3 transfers the output data D of semiconductor memory 1, now being applied to a data input terminal D of the output latch 3, to an output terminal as an output signal D.sub.out through an output terminal Q of the output latch 3. The data D is held in the output latch 3 at the fall of the clock pulse P2 and this data D, now in the output latch 3, is replaced, at the rise of the following clock pulse P3, with data which is being applied to the output terminal D.sub.o of the semiconductor memory 1 and consequently to the input terminal D of the output latch 3 at the instant the clock pulse P3 rises. As will be seen from the above, concurrently with setting the scan address bits A.sub.0 to A.sub.7 into the address latch 2 and consequent accessing of the semiconductor memory 1 at the rise of one clock pulse contained in the clock signal c, the same clock pulse is applied to the output latch 3 to assure that data read out of the semiconductor memory 1 by a clock pulse which immediately precedes the one clock pulse which was used to access the semiconductor memory 1 can be set into the output latch 3. This operation is repeated at a period of T1 by sequentially changing the contents of the scan address bits A.sub.0 to A.sub.7. The data appearing at the output latch 3 is fetched by an external device such as a service processor in which it is compared with a predetermined expected value to examine normality of the operation of the semiconductor memory 1.
Incidentally, the operation speed of the semiconductor memory 1 has been increased more and more. Especially where the delay time between input terminals A.sub.0 ' to A.sub.7 ' to output terminal D.sub.o of the semiconductor memory 1 amounts to, for example, about 5 ns, in order to diagnose the limit of the operation speed with the circuit operable as illustrated in FIG. 3, the repetition period for the clock pulse in the clock signal c must be about 5 ns and diagnostic data must be sent to the address latch 2 at this rate. If the operation speed of the semiconductor memory 1 is further increased, the repetition period for the clock pulse in the clock signal c must further be decreased. However, a clock pulse signal containing clock pulses of a short width which occur at such a repetition period is difficult to generate, giving rise to incompatibility of the existing diagnostic apparatus with performance of the semiconductor memory. The same is true for diagnosis of other logical circuits than the semiconductor memory such as LSI logical modules.
Although JP-A- No. 59-90067 may be mentioned as describing that identical diagnostic data stored in a plurality of memories are picked up on a time sharing basis to obtain a high speed diagnostic pattern, it contains no disclosure of clock signals and therefore can not accommodate itself to a higher speed diagnostic pattern as desired.